Testing memory modules such as single in-line memory modules (SIMMs) or double in-line memory modules (DIMMs) has become particularly important in a number of key applications. For instance, manufacturers of computer systems perform memory test suites to ensure installed memory will not fail when called upon to perform. One of ordinary skill will recognize that the term SIMM when used throughout this application similarly applies to and includes DIMMs.
Typical of conventional methods and apparatus for testing memory modules is the use of a test suite to test memory modules mounted on a CPU board. FIG. 1 shows a typical CPU board 104 included within a computer system 100. Computer System 100 generally includes a computer readable medium device 138 that reads and writes to a computer readable medium 140. Computer system 100 also includes an input device 142 and a display device 144 coupled to a CPU board 104 by a bus 143. CPU board 104 generally includes a processor 102, a memory bus 105 and a memory 103. As shown, memory 103 includes SIMM1 through SIMM 8 (106, 110, 114, 118, 122, 126, 130 and 134), where each SIMM is connected to memory bus 105 and is mounted to CPU board 104 via respective SIMM slot (146, 148, 150, 152, 154, 156, 158 and 160). Each SIMM accommodates surface mounted memory chips, such as DRAMs. For instance, SIMM1 106, through SIMM8 134, respectively, include a set of memory chips(108, 112, 116, 120, 124, 128, 132 and 136). As shown in FIG. 1, each set of memory chips preferably includes 18 memory chips. One of ordinary skill in the art will recognize that the number of memory chips installed on a given SIMM may vary depending upon a system's overall memory requirements and preferred system configuration.
Although conventional SIMM memory testing methods performed for example by memory test suite 109 have the ability to test SIMMs in parallel, each test can only accommodate the number of SIMMs mounted upon a particular CPU board. For example, since a typical CPU board 104 as shown in FIG. 1 includes 8 SIMMs (106, 110, 114, 118, 122, 126, 130, 134), not more than eight SIMMs can be tested in parallel at a given time. This limitation is particularly troublesome given the rapid increase in the amount of memory installed on new computer systems. Furthermore, because of this limitation, conventional memory testing systems do not provide a capacity for testing SIMM memory that meets the needs of users, such as computer system manufacturers.
New products such as computer systems that require memory and upgrades to current products continue to place more memory within these systems. Accordingly, the time required to test memory continues to increase. For example, the time needed to test increasingly larger memory units such as DRAMs that are installed on new products rise at a rate in excess of a linear function of the memory increase. For instance, as larger DRAMs are introduced into new products, the test time increase includes an additional 20% overhead on a mbyte/minute basis.
Also typical of conventional methods and apparatus for testing SIMMs is the immediate termination of testing when a first SIMM fails. For instance, if during conventional memory testing SIMM1 106 fails, testing immediately terminates without testing the remaining SIMMs. Therefore, re-executing memory testing is necessary to ensure errors are not present in the other SIMMs, including SIMM2 through SIMM 8 (110, 114, 118, 122, 126, 130 and 134). Because testing CPU board 104 with a conventional SIMM testing system could ultimately require numerous executions, such a conventional system unnecessarily wastes time and resources.
Conventional SIMM testing systems also do not include indicators that identify which memory chips are bad. For example, a conventional testing system for testing each of the eight SIMMs (106, 110, 114, 118, 122, 126, 130, 134) shown in FIG. 1, identifies which SIMMs are bad, but does not identify the specific memory chip(s) that caused the SIMM to fail. For instance, if during testing SIMM1 106 where to fail, a conventional SIMM testing system would not identify which of the eighteen memory chips 108, (e.g., DRAMs) are bad. Because of this limitation, when a SIMM failure occurs, conventional SIMM testing systems require a technician to review memory testing diagrams in order to debug which of the DRAMS led to the SIMM failure, thereby resulting in unnecessarily high debugging costs due in part to the expense of the technician's time on a problem that could otherwise be used in a more productive manner.
As a result, there has been a longfelt need for a SIMM testing system that performs parallel testing of a greater number of SIMMs than the number of SIMMs generally mountable on a CPU board, continues memory testing after a SIMM fails, and identifies the specific memory unit of a SIMM that is bad--requirements never previously met by conventional SIMM testing systems.